EACEN=EACEN_0, BOFFDONEMSK=BOFFDONEMSK_0, MRP=MRP_0, PREXCEN=PREXCEN_0, BTE=BTE_0, TSTAMPCAP=TSTAMPCAP_0, ERRMSK_FAST=ERRMSK_FAST_0, TIMER_SRC=TIMER_SRC_0, EDFLTDIS=EDFLTDIS_0, MBTSBASE=MBTSBASE_0, ISOCANFDEN=ISOCANFDEN_0, RRS=RRS_0
Control 2 register
| TSTAMPCAP | Time Stamp Capture Point 0 (TSTAMPCAP_0): The high resolution time stamp capture is disabled 1 (TSTAMPCAP_1): The high resolution time stamp is captured in the end of the CAN frame 2 (TSTAMPCAP_2): The high resolution time stamp is captured in the start of the CAN frame 3 (TSTAMPCAP_3): The high resolution time stamp is captured in the start of frame for classical CAN frames and in res bit for CAN FD frames |
| MBTSBASE | Message Buffer Time Stamp Base 0 (MBTSBASE_0): Message Buffer Time Stamp base is CAN_TIMER 1 (MBTSBASE_1): Message Buffer Time Stamp base is lower 16-bits of high resolution timer 2 (MBTSBASE_2): Message Buffer Time Stamp base is upper 16-bits of high resolution timerT |
| EDFLTDIS | Edge Filter Disable 0 (EDFLTDIS_0): Edge Filter is enabled 1 (EDFLTDIS_1): Edge Filter is disabled |
| ISOCANFDEN | ISO CAN FD Enable 0 (ISOCANFDEN_0): FlexCAN operates using the non-ISO CAN FD protocol. 1 (ISOCANFDEN_1): FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1). |
| BTE | Bit Timing Expansion enable 0 (BTE_0): CAN Bit timing expansion is disabled. 1 (BTE_1): CAN bit timing expansion is enabled. |
| PREXCEN | Protocol Exception Enable 0 (PREXCEN_0): Protocol Exception is disabled. 1 (PREXCEN_1): Protocol Exception is enabled. |
| TIMER_SRC | Timer Source 0 (TIMER_SRC_0): The Free Running Timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus. 1 (TIMER_SRC_1): The Free Running Timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus, or a different value as required. See the device specific section for details about the external time tick. |
| EACEN | Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes 0 (EACEN_0): Rx Mailbox filter’s IDE bit is always compared and RTR is never compared despite mask bits. 1 (EACEN_1): Enables the comparison of both Rx Mailbox filter’s IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. |
| RRS | Remote Request Storing 0 (RRS_0): Remote Response Frame is generated. 1 (RRS_1): Remote Request Frame is stored. |
| MRP | Mailboxes Reception Priority 0 (MRP_0): Matching starts from Legacy Rx FIFO or Enhanced Rx FIFO and continues on Mailboxes. 1 (MRP_1): Matching starts from Mailboxes and continues on Legacy Rx FIFO or Enhanced Rx FIFO . |
| TASD | Tx Arbitration Start Delay |
| RFFN | Number Of Legacy Rx FIFO Filters |
| BOFFDONEMSK | Bus Off Done Interrupt Mask 0 (BOFFDONEMSK_0): Bus Off Done interrupt disabled. 1 (BOFFDONEMSK_1): Bus Off Done interrupt enabled. |
| ERRMSK_FAST | Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames 0 (ERRMSK_FAST_0): ERRINT_FAST Error interrupt disabled. 1 (ERRMSK_FAST_1): ERRINT_FAST Error interrupt enabled. |